1. Field of the Invention
The present invention relates generally to a wafer package process, and more specifically to a wafer package process which applies flip-chip and molding technology.
2. Description of the Prior Art
As semiconductor fabrication technology grows more advanced, relevant techniques have to be developed in accordance with the changing requirements of the semiconductor devices. The fabrication process of a semiconductor device typically includes three stages. In the first stage, an epitaxy technique may be used for the formation of a semiconductor substrate. Semiconductor devices such as metal-oxide semiconductor (MOS) and multilevel interconnection are fabricated on the substrate in the second stage.
The third stage is the packaging process. It is now a leading trend devices or electronic products to be fabricated of thin, light, and small dimensions; that is, with a higher integration for semiconductor devices. Many package techniques such as chip scale package or multi-chip module (MCM) have been developed to obtain this high integration. The development of a fabrication technique with a line width of 0.18 μm has created great interest, and spurred intensive research to further decrease the package volume. Currently, one of the most important package techniques involves arranging more than one chip into a single package. In a multi-chip package, processor and memory chips, including dynamic random access memory (DRAM) and flash memory chips, can be packed together with a logic circuit into a single package, which reduces both the fabrication cost and the packaging volume. The signal transmission path can also be shortened to enhance the efficiency thereof, and this multi-chip IC packaging technology can be applied to a multi-chip system with variable functions and operation frequencies.